Example embodiments relate to delay locked loop (DLL) circuits, and particularly, to a DLL circuit that includes a frequency divider and multiphase generator (SRMG) having a self-referenced characteristics and allows a sigma-delta (ΣΔ) modulator to operate at a low frequency without generating false lock and glitch noise, and a semiconductor memory device including the DLL circuit.
Synchronous semiconductor memory devices, for example, double data rate synchronous DRAMs (DDR SDRAMs), may input or output data in synchronization with an external clock signal. For example, the synchronous semiconductor memory devices may use a DLL circuit in order to synchronize data with the external clock signal.
Conventional analog DLLs have a limited phase capture range, and conventional semi-digital DLLs have a limited phase resolution. Thus, conventional DLLs generate jitter.
In addition, conventional DLLs do not have a jitter transfer function as good as phase locked loops (PLLs), thus requiring a high over-sampling ratio.